Yi, Jiangfang


Yi, Jiangfang

Associate Professor

Research Interests: Computer architecture

Office Phone: 86-10-62765828-832

Email: yijiangfang@mprc.pku.edu.cn

Yi, Jiangfang is an assistant professor in the Department of Computer Science and technology, School of EECS. She obtained his B.Sc. from PLA Information Engineering University in 1999, and Ph.D. from Peking University in 2007 respectively. Her research interests include instruction level parallel, functional verification, cache coherence simulation and etc.

Dr. Yi devoted herself in UniCore series microprocessors, which are all made by Microprocessor Research and Development Center (MPRC). She was responsible for ISA design and micro-architecture implementation of UniCore-3 microprocessor. UniCore-3 is a 64-bit out-of-order superscalar microprocessor. It has 1~4 cores, 32iKB private L1 Cache and 2MiB shared L2 Cache. UniCore-3 applies hardware MOESI protocol and supports precise interrupt.

Dr. Yi has Beijing Science and technology projects, etc. Her research achievements are summarized as follows:

1)  Optimization mechanism of load/store execution: Aimed at performance and low energy consumption, proposed far store-load forwarding optimization based on store sequence number techniques. Instead of exact memory addresses, proposes address identifier to detect memory dependency. As a result, store-load forwarding could be advanced to the address calculation stage. It not only improves load execution performance but avoid unnecessary cache access.

2)   Functional test suite generation: combined machine learning with test suite generation, proposed a new methodology of functional test suite generation. Applied in verification of UniCore series microprocessors, it should reduce half of generation time which coverage is still up to 95%.

3)  Cache coherency simulation: proposed a simulation framework to validate a cache-coherence protocol implementation of a commercial 64-bit superscalar multiprocessor. It exploits multiple-level parallelism to accelerate validation without overheads among threads. The results demonstrate it has a 5.0x speedup than a traditional simulator.