Research Interests: Microprocessor architecture and design
Office Phone: 86-10-6276 5828-802
Tong, Dong is an associate professor in the Department of Computer Science and technology, School of EECS, and has been a faculty in Institute of Computer Architecture since 1999. He obtained his B.Sc., M.Sc. and Ph.D. from Harbin Institute of Technology in 1993, 1996 and 1999, respectively. His research interests include microprocessor architecture, memory systems, heterogeneous multicore/manycore, energy-efficiency computing.
Dr. Tong has published more than 100 research papers, and some of them were published in top-tier conferences, such as HPCA, PACT, ICS and ICCD. He has acquired more than ten patents on microprocessor and SoC design. He was awarded Peking University Teaching Achievement Award (2004), and other Teaching Grants several times.
Dr. Tong has finished many research projects including NSFC, 863 project, etc. His research achievements are summarized as follows:
1) Researches on Multi-core Memory Hierarchies. He proposed a method on cache behavior analysis, named “Optimal Replacement Algorithm Behavior Violation” for multi-core and last-level cache management. This idea has been used in his several researches on cache replacement, partition, prefetching and so on. He also proposed “Dynamic DRAM Bank Partition” technique to solve the interference problem in multi-core main memory controller by hardware-software co-design.
2) Researches Hardware-Software collaborative microarchitecture. He has rich research in compiling, operating system, virtual machine and microarchitecture collaborative design. The key factor is that system software optimize programs based on some hardware features and send hints to hardware such as branch predictor, for high performance and low power.
3) Researches on Energy-Efficiency Microprocessor. He has long been engaged in the research and development of microarchitecture and SoC design. The chip products he involved have been deployed several hundred thousand units. He has proposed a technique, named “virtual address speculatively load forwarding”, which can significantly reduce the delay of load instructions execution in an out-of-order processor.