Lu, Junlin


Lu, Junlin

Associate Professor

Research Interests: Computer architecture

Office Phone: 86-10-6276 5828-831


Lu, Junlin is an assistant professor in the Department of Computer Science and technology, School of EECS, and has served as the Deputy Director of Institute of Computer Architecture since 2011. He obtained his B.Sc. from Peking University in 2002, and Ph.D. from Peking University in 2009 respectively. His research interests include on computer architecture, heterogeneous system-on-chip, memory hierarchy, on-chip communication and software/hardware co-design.

Dr. Lu focuses on innovating indigenous microprocessor (CPU) and computer. He has published research papers and held patents in this field. As a lecturer of two fundamental courses, Introduction to Computer Systems and Computer Organization, he got several teaching excellence awards. He is also the vice secretary of the ACM SIGCSE China Chapter. Meanwhile, he is serving as a member of CE2016 Steering Committee in ACM, which is responsible for compiling CE2016 Curriculum Guidelines.

Dr. Lu has joined more than ten research projects, including National Science and Technology Major Project, National 863 Program, etc. His research achievements are summarized as follows:

1)  On-chip communication: On-chip communication has been a bottleneck for a large SoC to realize its expected performance. Hence the communication-focused design methodology is the first choice for current SoC design. One major research topic is the most popular solution of on-chip communication architecture, network-on-chip(NoC). Some new techniques have been proposed on communication interface, debug support, arbitration algorithm and NoC routing. These techniques together will help resolve the challenges to on-chip communication architecture in SoCs.

2)  Memory hierarchy: Memory is the critical component of all computing systems. Especially in multiprocessor systems, the memory accesses of different applications interfere with each other in the DRAM memory. One major research topic is the bank-level parallelism of individual applications, and increasing the system performance and individual application performances.

3)  Heterogeneous SoC:  The heterogeneous SoC is based on the UniCore CPU and an x86 CPU. UniCore instruction set architecture is indigenous. It’s a RISC architecture. The x86 technology is transferred from AMD as the most significant technology overseas transfer from the US. This cross-disciplinary practice has also fostered many innovations in microprocessor architecture, optimizing compilers, low power design, functional verification, physical design, and so on.