Research Interests: Computer architecture, compiler optimization
Liu, Xianhua is an associate professor in the Department of Computer Science and Technology, School of EECS. He obtained his B.E. from Tsinghua University in 2000, and Ph.D. from Peking University in 2007 respectively. His research interests include compiler optimization and hardware/software co-design.
Dr. Liu has published 20+ research papers in top-tier conferences, such as ICCD, DATE, FPGA, ICS, ICPP and VEE. He serves in working groups of several industry standards on cloud computing and embedded control systems, also acts as the technical program committee member of the National Engineering Laboratory for E-government Cloud Computing Application Technology. Dr. Liu is also responsible for compiler design courses in the Department of C.S., Peking University.
Dr. Liu has led or attended more than ten research projects including NSFC, National S&T Major Project, 863 project, etc. His main research achievements are as follows:
1) Dr. Liu and others has jointly developed China’s first 16/32-bit indigenous microprocessor following the top-down design approach. The computers using PKU’s UniCore CPU have been widely used in many fields all over China. Dr. Liu led the compilation toolchain group to support the whole system to run smoothly and correctly, which includes BIOS, OS kernel, X-Windows and other key applications.
2) Dr. Liu has proposed a number of compiler analysis and collaborative optimization methods, which abstractly describes the microarchitecture to help compiler get the hardware constraint information in the design flow. High-level language semantics are more effectively transmitted to lower-level circuit descriptions, which can effectively guide the design flow and provide strong support for the instruction-level optimization. Dr. Liu gives several extension solutions and optimization strategies for processor design, which can be applied in different application scenarios. These techniques may better meet the requirements of performance, power consumption and cost constraints, and can get an optimized design process reference.