Cheng, Xu


Cheng, Xu


Research Interests: Microprocessor design, HW/SW Co-Design

Office Phone: 86-10-6276 5828-688


Cheng, Xu is a professor in the Department of Computer Science and Technology, School of EECS, and has served as Assistant President of Peking University since 2010, Dean of the Advanced Technology Institute since 2011, and the Director of Microprocessor Research and Development Center (MPRC) and Director of Institute of Computer Architecture since 2002. He obtained his Bachelor’s Degree in 1988, Master’s Degree in 1991 and Ph.D. in 1994 from Harbin Institute of Technology respectively. His research interests include high performance microprocessor, System-on-Chip, instruction level parallelism, HW/SW co-design and compiler optimization.

He is the member of Advisory Committee for State Informatization (ACSI) and has been serving as a number of national and ministry-level advisory committees in China.

He has published more than 100 research papers in conferences and journals, such as HPCA, ICS, DAC, ICCD, FPGA, ISLPED, PACT, DATE, ASP-DAC, etc.

He was awarded Peking University Outstanding Teachers, Henry Fok Young Teachers Award (1997), Ten Scientific and Technological Progress of Chinese Universities (1999), The Ministry of Education Trans-century Talents(2002), The most respected of Peking University "TOP 10 Best Teacher"(2003), Beijing "May 4th medal"(2004).

Dr. Cheng has led more than 30 research projects including NSFC, 863 project, National Science and Technology Major Projects, etc. His research achievements are summarized as follows:

1)  Microprocessors Design: He acted as pioneer in designing microprocessors with indigenous instruction set, by using the hardware / software co-design methodology in China. In 1999, he was in charge of developing the first hardware / software co-design environment supporting the microprocessor top-down design and the 16-bit microprocessor with indigenous instruction set in China. In January 2001, he took charge of the development of the first microprocessor in China which supported 32-bit and 16-bit dual complete instruction sets.

2)  SoC Design: In 2006, Prof. Cheng’s team launched the project “Super-K” designing the next generation SoC, which would be the heart of a 3C computer also designed at MPRC. Super-K is characterized by “a single-chip solution”, which would cut down cost to an extremely low level. More importantly, Super-K is an effective way to improve the performance and power profile. In 2009, the mass production of the first generation of Super-K SoC Product (PKUNITY SoC) began. At present, a series of PKUNITY SoCs are widely used in the fields of education and information security.